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1/61 july 1999 n high performance cpu 16-bit cpu with 4-stage pipeline. 16-bit cpu with 4 stage pipeline 100ns instruction cycle time at 20mhz cpu clock 500ns multiplication (16*16 bit) 1 m s division (32/16 bit) enhanced boolean bit manipulation facilities additional instructions to support hll and operating systems single-cycle context switching support n memory organization 2k byte on-chip internal ram 2k byte on-chip extension ram 128k byte on-chip flash memory flash with 4 independently erasable banks n fast and flexible bus programmableexternalbus character- istics for different address ranges 8-bit or 16-bit external data bus. multiplexed or de-multiplexed exter- nal address/data buses five programmablechip-select signals. hold and hold-acknowledge bus arbi- tration support n fail-safe protection programmable watchdog timer n on-chip can 2.0b interface n on-chip bootstrap loader n interrupt 8-channel pec for single cycle, inter- rupt driven data transfer 16-priority-level interrupt system with 56 sources, sample-rate down to 50ns n timers two multi-functional general-purpose timer units with 5 timers two 16-bit capture/compare units n a/d converter 16-channel 10-bit 9.7 m s conversion time n clock generation on-chip pll. direct clock input n up to 111 general purpose i/o lines programmable threshold (hysteresis) n idle and power down modes idle current <70ma power down supply current <100 m a. n 4-channel pwm unit n serial channels synchronous/asynch serial channel. high speed synchronous channel n electrical characteristics power - 5v 10% n development support c-compilers, macro-assembler packages, emulators, evaluation boards, hll-de- buggers, simulators, logic analyzer dis- assemblers, programming boards n package option 144-pin pqfp package pqfp144 (28 x 28 mm) (plastic quad flat pack) p.0 p.1 p.4 p.6 p.5 p.3 p.2 gpt2/gpt1 asc usart brg cpu-core internal ram wdog interrupt controller pec can p.7 p.8 ebc 10-bit adc brg ssc pwm capcom2 capcom1 osc. xram flash 128kbyte ST10F167 16-bit mcu with 128kbyte flash memory this is advance information on a new product now in development or undergoing evaluation. details are subject to change without notice.
ST10F167 2/61 table of contents page i introduction ......................................................................................................... 4 ii pin data.................................................................................................................... 5 iii functional description.................................................................................... 10 iv memory organization........................................................................................ 11 v flash memory ................................................................................... .................... 12 v.1 flash programming and erasing .................................................................. 12 v.2 flash control register (fcr) ........................................................................ 12 v.2.1 flash memory security ................................................................................................ 14 vi external bus controller............................................................................... 16 vii central processing unit (cpu) ...................................................................... 17 viii interrupt system ................................................................................................ 18 ix capture/compare (capcom) units................................................................ . 21 x general purpose timer (gpt) unit ................................................................ 22 x.1 gpt1 ........................................................................................................................ ... 22 x.2 gpt2 ........................................................................................................................ ... 22 xi pwm module ................ ........................................................................................... 25 xii parallel ports ......... ........................................................................................... 26 xiii a/d converter...................................... ................................................................. 26 xiv serial channels .............................................................................. .................... 27 xiv.1 asco ...................................................................................................................... .... 27 xiv.2 high speed synchronous serial channel (ssc) ...................................... 27 xv can module ............................................................................................................ 28 xvi watchdog timer................................................................................................... 28 xvii instruction set .................................................................................................... 29 xviii bootstrap loader............................. ................................................................. 30 xix special function registers............................................................................ 31 xx electrical characteristics ......................................................................... . 37 xx.1 absolute maximum ratings ............. ................................................................. 37 xx.2 parameter interpretation.............................................................................. 37 xx.3 dc characteristics ............................................................................................ 37
ST10F167 3/61 table of contents (continued) page xx.4 a/d converter characteristics.................................................................... 39 xx.5 ac characteristics............................................................................................. 40 xx.5.1 test waveforms ........................................................................................................... 4 0 xx.5.2 definition of internal timing .......................................................................................... 41 xx.5.3 direct drive.............................................................................................................. ... . 41 xx.5.4 phase locked loop ...................................... ................................................................. 41 xx.5.5 external clock drive xtal1 ........................................................................................ . 42 xx.5.6 memory cycle variables............................................................................................... 43 xx.5.7 multiplexed bus ............................................................. .............................................. 43 xx.5.8 demultiplexed bus....................................................................................................... 49 xx.5.9 clkout and ready.............................................................................. .................... 55 xx.5.10 external bus arbitration............................................................................................... 57 xxi package mechanical data ................................ .............................................. 59 xxii ordering information ....................................................................................... 60 xxiii revision history .................................................................................................. 60
ST10F167 4/61 i - introduction the ST10F167 is a derivative of the stmicro- electronics 16-bit single-chip cmos microcon- trollers. it combines high cpu performance with high peripheral functionality and enhanced i/o capabilities. it also provides on-chip high-speed ram and clock generation via pll. figure 1 : logic symbol xtal1 rstin xtal2 rstout nmi ea ready ale rd wr/wrl port 5 16-bit port 6 8-bit port 4 8-bit port 3 15-bit port 2 16-bit port 1 16-bit port 0 16-bit v dd v ss ST10F167 port 7 8-bit port 8 8-bit v aref v agnd v pp this is advance information on a new product now in development or undergoing evaluation. details are subject to change without notice.
ST10F167 5/61 ii - pin data figure 2 : pin out ST10F167 p6.0/cs0 p6.1/cs1 p6.2/cs2 p6.3/cs3 p6.4/cs4 p6.5/hold p6.6/hlda p6.7/breq p8.0/cc16io p8.1/cc17io p8.2/cc18io p8.3/cc19io p8.4/cc20io p8.6/cc22io p8.7/cc23io v dd v ss p7.0/pout0 p7.1/pout1 p7.2/pout2 p7.3/pout3 p8.5/cc21io v pp p7.4/cc28i0 p7.5/cc29i0 p7.6/cc30i0 p7.7/cc31i0 p5.0/an0 p5.1/an1 p5.2/an2 p5.3/an3 p5.4/an4 p5.5/an5 p5.6/an6 p5.7/an7 p5.8/an8 p5.9/an9 p0h.0/ad8 p0l.7/ad7 p0l.6/ad6 p0l.5/ad5 p0l.4/ad4 p0l.3/ad3 p0l.2ad2 p0l.1/ad1 p0l.0/ad0 ea ale ready wr/wrl rd v ss v dd p4.7/a23 p4.6/a22/can_txd p4.5/a21/can_rxd p4.4/a20 p4.3/a19 p4.2/a18 p4.1/a17 p4.0/a16 v ss v dd p3.15/clkout p3.13/sclk p3.12/bhe/wrh p3.11/rxd0 p3.10/txd0 p3.9/mtsr p3.8/mrst p3.7/t2in p3.6/t3in v aref v agnd p5.10/an10/t6eud p5.11/an11/t5eud p5.12/an12/t6in p5.13/an13/t5in p5.14/an14/t4eud p5.15/an15/t2eud v ss v dd p2.0/cc0io p2.1/cc1io p2.2/cc2io p2.3/cc3io p2.4/cc4io p2.5/cc5io p2.6/cc6io p2.7/cc7io v ss v dd p2.8/cc8io/ex0in p2.9/cc9io/ex1in p2.10/cc10ioex2in p2.11/cc11ioex3in p2.12/cc12io/ex4in p2.13/cc13io/ex5in p2.14/cc14io/ex6in p2.15/cc15io/ex7in/t7in p3.0/t0in p3.1/t6out p3.2/capin p3.3/t3out p3.4/t3eud p3.5/t4in v ss v dd v ss nmi v dd rstout rstin v ss xtal1 xtal2 v dd p1h.7/a15/cc27io p1h.6/a14/cc26io p1h.5/a13/cc25io p1h.4/a12/cc24io p1h.3/a11 p1h.2/a10 p1h.1/a9 p1h.0/a8 v ss v dd p1l.7/a7 p1l.6/a6 p1l.5/a5 p1l.4/a4 p1l.3/a3 p1l.2/a2 p1l.1/a1 p1l.0/a0 p0h.7/ad15 p0h.6/ad14 p0h.5/ad13 p0h.4/ad12 p0h.3/ad11 p0h.2/ad10 p0h.1/ad9 v ss v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
ST10F167 6/61 table 1 : pin list symbol pin type function p6.0 p6.7 1 - 8 i/o port 6 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 6 outputs can be configured as push/pull or open drain drivers. the following port 6 pins also serve for alternate functions: 1 ... 5 6 7 8 o ... o i o o p6.0 cs0 chip select 0 output ... ... ... p6.4 cs4 chip select 4 output p6.5 hold external master hold request input p6.6 hlda hold acknowledge output p6.7 breq bus request output p8.0 p8.7 9 - 16 i/o port 8 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 8 outputs can be configured as push/pull or open drain drivers. the input threshold of port 8 is select- able (ttl or special). the following port 8 pins also serve for alternate functions: 9 ... 16 i/o ... i/o p8.0 cc16io capcom2: cc16 capture in/compare out ... ... ... p8.7 cc23io capcom2: cc23 capture in/compare out p7.0 p7.7 19 -26 i/o port 7 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 7 outputs can be configured as push/pull or open drain drivers. the input threshold of port 7 is select- able (ttl or special). the following port 7 pins also serve for alternate functions: 19 ... 22 23 ... 26 o ... o i/o ... i/o p7.0 pout0 pwm channel 0 output ... ... ... p7.3 pout3 pwm channel 3 output p7.4 cc28io capcom2: cc28 capture in/compare out ... ... ... p7.7 cc31io capcom2: cc31 capture in/compare out p5.0 p5.15 27-36 39-44 i i port 5 is a 16-bit input-only port with schmitt-trigger characteristics. the pins of port 5 also serve as the (up to 16) analog input channels for the a/ d converter, where p5.x equals anx (analog input channel x), or they serve as timer inputs: 39 40 41 42 43 44 i i i i i i p5.10 t6eud gpt2 timer t6 ext.up/down control input p5.11 t5eud gpt2 timer t5 ext.up/down control input p5.12 t6in gpt2 timer t6 count input p5.13 t5in gpt2 timer t5 count input p5.14 t4eud gpt1 timer t4 ext.up/down control input p5.15 t2eud gpt1 timer t2 ext.up/down control input ii - pin data (continued)
ST10F167 7/61 p2.0 p2.15 47-54 57-64 i/o port 2 is a 16-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 2 outputs can be configured as push/pull or open drain drivers. the input threshold of port 2 is select- able (ttl or special). the following port 2 pins also serve for alternate functions: 47 ... 54 57 ... 64 i/o ... i/o i/o i ... i/o i i p2.0 cc0io capcom: cc0 capture in/compare out ... ... ... p2.7 cc7io capcom: cc7 capture in/compare out p2.8 cc8io capcom: cc8 capture in/compare out ex0in fast external interrupt 0 input ... ... ... p2.15 cc15io capcom: cc15 capture in/compare out ex7in fast external interrupt 7 input t7in capcom2 timer t7 count input p3.0- p3.13, p3.15 65-70, 73-0, 81 i/o i/o i/o port 3 is a 15-bit (p3.14 is missing) bidirectional i/o port. it is bit-wise pro- grammable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 3 outputs can be configured as push/pull or open drain drivers. the input threshold of port 3 is selectable (ttl or special). the following port 3 pins also serve for alternate functions: 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 i o i o i i i i i/o i/o i/o o o i/o o p3.0 t0in capcom timer t0 count input p3.1 t6out gpt2 timer t6 toggle latch output p3.2 capin gpt2 register caprel capture input p3.3 t3out gpt1 timer t3 toggle latch output p3.4 t3eud gpt1 timer t3 external up/down control input p3.5 t4in gpt1 timer t4 input for count/gate/reload/capture p3.6 t3in gpt1 timer t3 count/gate input p3.7 t2in gpt1 timer t2 input for count/gate/reload/capture p3.8 mrst ssc master-receive/slave-transmit i/o p3.9 mtsr ssc master-transmit/slave-receive o/i p3.10 txd0 asc0 clock/data output (asyn./syn.) p3.11 rxd0 asc0 data input (asyn.) or i/o (syn.) p3.12 bhe ext. memory high byte enable signal, wrh ext. memory high byte write strobe p3.13 sclk ssc master clock output/slave clock input p3.15 clkout system clock output (=cpu clock) p4.0 p4.7 85-92 i/o port 4 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. in case of an external bus config- uration, port 4 can be used to output the segment address lines : 85 90 91 92 o o i o o o p4.0 a16 least significant segment address line p4.5 a21 segment address line can_rxd can receive data input p4.6 a22 segment address line, can_txd can transmit data output p4.7 a23 most significant segment address line rd 95 o external memory read strobe. rd is activated for every external instruc- tion or data read access. table 1 : pin list (continued) symbol pin type function ii - pin data (continued)
ST10F167 8/61 wr/wrl 96 o external memory write strobe. in wr-mode this pin is activated for every external data write access. in wrl-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in register syscon for mode selection. ready/ready 97 i ready input. the active level is programmable. when the ready function is enabled, the selected inactive level at this pin during an external mem- ory access will force the insertion of memory cycle time waitstates until the pin returns to the selected active level. ale 98 o address latch enable output. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. ea 99 i external access enable pin. a low level at this pin during and after reset forces the ST10F167 to begin instruction execution out of external mem- ory. a high level forces execution out of the internal flash memory. port0: p0l.0-p0l.7, p0h.0-p0h.7 100-107, 108, 111-117 i/o port 0 consists of the two 8-bit bidirectional i/o ports p0l and p0h. it is bit-wise programmable for input or output via direction bits. for a pin con- figured as input, the output driver is put into high-impedance state. in case of an external bus configuration, port 0 serves as the address (a) and address/data (ad) bus in multiplexed bus modes and as the data (d) bus in demultiplexed bus modes. demultiplexed bus modes: data path width : 8-bit 16-bit p0l.0 p0l.7 : d0 d7 d0 - d7 p0h.0 p0h.7 : i/o d8 - d15 multip lexed bus modes: data path width : 8-bit 16-bit p0l.0 p0l.7 : ad0 ad7 ad0 - ad7 p0h.0 p0h.7 : a8 - a15 ad8 - ad15 port1: p1l.0-p1l.7, p1h.0-p1h.7 118-125, 128-135 i/o port 1 consists of the two 8-bit bidirectional i/o ports p1l and p1h. it is bit-wise programmable for input or output via direction bits. for a pin con- figured as input, the output driver is put into high-impedance state. port 1 is used as the 16-bit address bus (a) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. the following port1 pins also serve for alternate functions: 132 133 134 135 i i i i p1h.4 cc24io capcom2: cc24 capture input p1h.5 cc25io capcom2: cc25 capture input p1h.6 cc26io capcom2: cc26 capture input p1h.7 cc27io capcom2: cc27 capture input xtal1 138 i input to the oscillator amplifier and input to the internal clock generator xtal2 137 o output of the oscillator amplifier circuit. to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. rstin 140 i reset input with schmitt-trigger characteristics. a low level at this pin for a specified duration while the oscillator is running resets the ST10F167. an internal pullup resistor permits power-on reset using only a capacitor connected to v ss . in bidirectional reset mode (enabled by setting bit bdrsten in syscon register), the rstin line is pulled low for the duration of the internal reset sequence. table 1 : pin list (continued) symbol pin type function ii - pin data (continued)
ST10F167 9/61 rstout 141 o internal reset indication output. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog-timer reset. rstout remains low until the einit (end of initialization) instruc- tion is executed. nmi 142 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. if bit pwdcfg = `0' in syscon register, when the pwrdn (power down) instruction is exe- cuted, the nmi pin must be low in order to force the ST10F167 to go into power down mode. if nmi is high and pwdcfg ='0', when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. v aref 37 - reference voltage for the a/d converter. v agnd 38 - reference ground for the a/d converter. v pp /rpd 84 - flash programming voltage (ST10F167 only). this pin accepts the programming voltage for ST10F167 derivatives with on-chip flash memory. it is used also as the timing pin for the return from powerdown circuit and power-up asynchronous reset. v dd 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 - digital supply voltage: = + 5 v during normal operation and idle mode. > + 2.5 v during power down mode v ss 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 - digital ground. table 1 : pin list (continued) symbol pin type function ii - pin data (continued)
ST10F167 10/61 iii - functional description the architecture of the ST10F167 combines advantages of both risc and cisc processors and an advanced peripheral subsystem. the following block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F167. figure 3 : block diagram port 0 port 1 port 4 port 6 port 5 port 3 port 2 gpt1 gpt2 asc usart brg internal flash memory cpu-core internal ram watchdog interrupt controller 32 16 pec 16 16 can port 7 port 8 external bus 10-bit adc brg ssc pwm capcom2 capcom1 osc. xram 16 controller 16 8 16 16 16 8 15 8 8 16
ST10F167 11/61 iv - memory organization the memory space of the ST10F167 is configured in a von-neumann architecture. code memory, data memory, registers and i/o ports are orga- nized within the same linear address space of 16m byte. the entire memory space can be accessed bytewise or wordwise. particular por- tions of the on-chip memory have additionally been made directly bit addressable. the ST10F167 provides 128k byte of on-chip flash memory. 2k byte of on-chip internal ram stores user defined variables for the system stack, general purpose register banks and even for code. a reg- ister bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, , rl7, rh7) so-called general purpose registers (gprs). 1024 byte (2 * 512 byte) of the address space are reserved for the special function register areas (sfr space and esfr space). sfrs are word- wide registers which are used for controlling and monitoring functions of the different on-chip units. unused sfr addresses are reserved for other/ future members of the st10 family. 2k byte of on-chip extension ram (xram) are provided to store user data, user stacks or code. the xram is accessed like external memory and cannot be used for the system stack or register banks, and is not bit-addressable. the xram allows 16-bit accesses with maximum speed. in order to meet the needs of designs where more memory is required than is provided on chip, up to 16m byte of external ram and/or rom can be connected to the microcontroller.
ST10F167 12/61 v - flash memory the ST10F167 provides 128k byte of on-chip, electrically erasable and re-programmable flash eprom. the flash memory is organized in 32 bit wide blocks. double word instructions can be fetched in one machine cycle. the flash memory can be used for both code and data storage. it is organised into four banks of sizes 8k, 24k, 48k and 48k byte. each of these banks can be erased independently. this prevents unnecessary re-pro- gramming of the whole flash memory when only partial re-programming is required. the first 32k byte of the flash memory are located in segment 0 (0h to 007fffh) during reset, and include the reset and interrupt vectors. the rest of the flash memory is mapped in segments 1 and 2 (018000h to 02ffffh). for flexibility, the first 32k byte of the flash memory may be remapped to segment 1 (010000h to 017fffh) during initialization. this allows the interrupt vec- tors to be programmed from the external memory, while retaining the common routines and constants that are programmed into the flash memory. v.1 - flash programming and erasing the flash memory is programmed using the presto f program write algorithm. erasure of the flash memory is performed in the program mode using the presto f erase algorithm. timing of the write/erase cycles is automatically generated by a programmable timer and comple- tion is indicated by a flag. a second flag indicates that the v pp voltage was correct for the whole pro- gramming cycle. this guarantees that a good write/erase operation has been carried out. v.2 - flash control register (fcr) in the standard operation mode, the flash mem- ory can be accessed in the same way as the nor- mal mask-programmable on-chip rom. all appropriate direct and indirect addressing modes can be used for reading the flash memory. all programming or erase operations are con- trolled via a 16-bit register, the fcr. the fcr is not an sfr or gpr. to prevent inadvertent writing to the flash memory, the fcr is locked and inactive during the standard operation mode. the flash memory writing mode must be entered before a valid access to the fcr is provided. this is done via a special key code instruction sequence. the fcr is virtually mapped into the active address space of the flash memory. it can only be accessed with direct 16-bit (mem) addressing modes. since the fcr is neither byte, nor bit-addressable, only word operand instructions can be used for fcr accesses. by default, the fcr can be accessed with any even address from 000000h to 07fffeh and 018000h to 02fffeh. if the first 32k byte block of the flash memory is mapped to segment 1, the corresponding even fcr addresses are 010000h to 017ffeh. note that dpp referencing and dpp contents must be considered for fcr accesses. if an fcr access is attempted via an odd address, an illegal operand access hardware trap will occur. fcr flash control register: reset condition: 0000h (read). table 2 : flash memory bank addresses bank addresses (segment 0) size (byte) 0 1 2 3 000000h to 07fffh and 018000h to 01bfffh 01c000h to 027fffh 028000h to 02dfffh 02e000h to 02ffffh 48k 48k 24k 8k table 3 : flash parameters parameter units min typical max word programming time m sec 12.8 12.8 1250 bank erasing time sec 0.5 30 endurance cycles 1000 flash v pp volts 11.4 12.6
ST10F167 13/61 v - flash memory (continued) table 4 : flash control register bit definition bit number & name description b15 = fwmset flash writing mode set. this bit is set to o1o automatically once the flash writing mode is entered. to exit from the flash writing mode, fwmset must be set to o0o. since only word values can be written to fcr, care must be taken that fwmset is not cleared inadvertently. therefore, for any command written to fcr (except for the return to the flash standard mode), fwmset must be set to o1o. reset condition of fwmset is o0o. b14-b10 these bits are reserved for future development, they must be written to o0o. b9-b8 = be0,1 bank erase select. select the flash memory bank to be erased. the physical addresses of bank 0 depends on the which flash memory map has been chosen. in flash operating modes, other than the erasing mode, these bits are not significant. at reset be1,0 are set to o00o. b7 = wdww word/double word write. determines the word width used for programming operations: 16-bit (wdww = 0) or 32-bit (wdww = o1o). in flash operation modes, other than the programming mode, this bit is not significant. at reset, wdww is set to a0o. b6-b5 = ckctl0,1 flash timer clock con- trol. control the width (tprg) of the programming or erase pulses applied to the flash memory cells during the operation. tprg varies in an inverse ratio to the clock frequency. to avoid putting the flash memory under critical stress conditions, the width of one single program- ming or erase pulse and the programming or erase time, must not exceed defined values. thus the maximum number of programming or erase attempts, depends on the system clock frequency. reset state: 00. b4 = vppriv v pp revelation bit. read-only bit reflects the state of the v pp voltage in the flash writing mode. if vppriv is set to o0o, this indicates that v pp is below the threshold necessary for reliable programming. the normal reaction to this indication is to check the v pp power supply and to then repeat the intended operation. if the v pp voltage is above a sufficient margin, vppriv will be set to o1o. the reset state of the vppriv bit depends on the state of the external v pp voltage at the v pp pin. b3 = fcvpp flash v pp control bit. read-only bit indicates that the v pp voltage fell below the valid threshold value during a flash programming or erase operation. if fcvpp is set to o1o after such an operation has finished, it can mean that the operation was not successful. the v pp power supply should be checked and the operation repeated. if fcvpp is set to o0o, no critical discontinuity in v pp occurred. at reset fcvpp is set to o0o. b2 = fbusy flash busy bit. read-only bit indicates that a flash programming or erase operation is in progress. fbusy is set to o1o by hardware, as soon as the programming or erase command is given. at reset fbusy is set to o0o. note that this bit position is also occupied by the write-only bit rprot. b2 = rprot protection enable bit. this bit set at '1', and ed with the otp protection bit, disables any access to the flash, by instructions fetched from the external memory space, or from the internal ram. this write-only bit, is only significant if the general flash memory protection is enabled. if the protection is enabled, the setting of rprot determines whether the flash protection is active (rprot=o1o) or inactive (rprot=o0o). rprot is the only fcr bit which can be modified even in the flash standard operation mode, but only by an instruction executed from the flash memory itself. at reset, rprot is set to o1o. note that this bit position is also occupied by the read-only bit fbusy. b1 = fee flash erase/program selection. selects the flash write operation to be performed: erase (fee=o1o) or programming (fee=o0o). together with bits fwe and fwmset, bit fee determined the operation mode of the flash memory. note that setting bits fwe and fee causes the corresponding flash operation mode to be selected but does not launch the execution of the selected operation. if bit fwe was set to o0o, the setting of fee is insignificant. at reset, fee is set to o0o. b0 = fwe flash write/read enable. this bit determines whether flash write operations are enabled (fwe=1) or disabled (fwe=0). by definition, a flash write operation can be either programming or erasure. together with bits fee and fwmset, bit fwe determines the operation mode of the flash memory. note that setting bits fwe and fee causes the corresponding flash operation mode to be selected but does not launch the execution of the selected operation. if bit fwe was set to o1o, any read access on a flash memory location means a particular pro- gram-verify or erase-verify read operation. flash write operations are disabled at reset.
ST10F167 14/61 v.2.1 - flash memory security security and reliability have been enhanced by built-in features: a key code sequence is used to enter the write/erase mode preventing false write cycles, a programmable option (set by the pro- gramming board) prevents access to the flash memory from the internal ram or from external memory. if the security option is set, the flash memory can only be accessed from a program within the flash memory area. this protection can only be disabled by instruc- tions executed from the flash memory. figure 4 : presto f write algorithm =0 pcount=pnmax? pcount=pcount+1 vr02057a v - flash memory (continued)
ST10F167 15/61 figure 5 : presto f erase algorithm =0 pcount=enmax? pcount=pcount+1 vr02057b v - flash memory (continued)
ST10F167 16/61 vi - external bus controller all of the external memory accesses are per- formed by the on-chip external bus controller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of four different external memory access modes: 16-/18-/20-/24-bit addresses, 16-bit data, demultiplexed 16-/18-/20-/24-bit addresses, 16-bit data, multiplexed 16-/18-/20-/24-bit addresses, 8-bit data, multiplexed 16-/18-/20-/24-bit addresses, 8-bit data, demultiplexed in the demultiplexed bus modes, addresses are output on port1 and data is input/output on port0. in the multiplexed bus modes both addresses and data use port0 for input/output. important timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read/write delay) have been made programmable. this gives the choice of a wide range of external of memories and external peripherals. in addition, different address ranges may be accessed with different bus characteristics. up to 5 external cs signals (4 windows plus default) can be generated in order to save external glue logic. access to very slow memories is supported via a particular `ready' function. a hold/hlda protocol is avail- able for bus arbitration. for applications which require less than 16m byte of external memory space, this address space can be restricted to 1m byte, 256k byte or to 64k byte. in this case port 4 outputs four, two or no address lines. if an address space of 16m byte is used, it outputs all 8 address lines.
ST10F167 17/61 vii - central processing unit (cpu) the cpu includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (alu). dedicated sfrs have been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. most of the ST10F167's instructions can be exe- cuted in one instruction cycle which requires 100ns at 20mhz cpu clock. for example, shift and rotate instructions are always processed in one machine cycle independent of the number of bits to be shifted. all multiple-cycle instructions have been optimized for speed: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. the `jump cache' pipeline optimization, reduces the execu- tion time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. the cpu includes an actual register context. this consists of up to 16 wordwide gprs which are physically allocated within the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu at a time. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 2048 byte is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. figure 6 : cpu block diagram 32 internal ram 2k byte general purpose registers r0 r15 mdh mld barrel-shift mul./div.-hw bit-mask gen. alu 16-bit cp sp stkov stkun exec. unit instr. ptr instr. reg 4-stage pipeline psw syscon buscon 0 buscon 1 buscon 2 buscon 3 buscon 4 addrsel 1 addrsel 2 addrsel 3 addrsel 4 data pg. ptrs code seg. ptr. cpu 256k byte flash memory 16 16 bank n bank i bank 0
ST10F167 18/61 viii - interrupt system with an interrupt response time from 250ns to 600ns (in the case of internal program execution), the ST10F167 reacts quickly to the occurrence of non-deterministic events the architecture of the ST10F167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. any of these interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in a standard interrupt service, program execution is suspended and a branch to the interrupt vector table is performed. for a pec service, just one cycle is `stolen' from the current cpu activity. a pec service is a single byte or word data transfer between any two memory locations with an addi- tional increment of either the pec source or the destination pointer. an individual pec transfer counter is decremented for each pec service, except for the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are suited to, for example, the transmission or reception of blocks of data. the ST10F167 has 8 pec channels, each of which offers fast interrupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. via its related register, each source can be programmed to one of sixteen interrupt priority levels. once having been accepted by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedi- cated vector location. fast external interrupt inputs are provided to ser- vice external interrupts with high precision requirements. these fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). software interrupts are supported by means of the `trap' instruction in combination with an individ- ual trap (interrupt) number. table 5 shows all the available ST10F167 inter- rupt sources and the corresponding hard- ware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. table 5 : list of interrupt sources source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number capcom register 0 cc0ir cc0ie cc0int 00'0040h 10h capcom register 1 cc1ir cc1ie cc1int 00'0044h 11h capcom register 2 cc2ir cc2ie cc2int 00'0048h 12h capcom register 3 cc3ir cc3ie cc3int 00'004ch 13h capcom register 4 cc4ir cc4ie cc4int 00'0050h 14h capcom register 5 cc5ir cc5ie cc5int 00'0054h 15h capcom register 6 cc6ir cc6ie cc6int 00'0058h 16h capcom register 7 cc7ir cc7ie cc7int 00'005ch 17h capcom register 8 cc8ir cc8ie cc8int 00'0060h 18h capcom register 9 cc9ir cc9ie cc9int 00'0064h 19h capcom register 10 cc10ir cc10ie cc10int 00'0068h 1ah capcom register 11 cc11ir cc11ie cc11int 00'006ch 1bh capcom register 12 cc12ir cc12ie cc12int 00'0070h 1ch capcom register 13 cc13ir cc13ie cc13int 00'0074h 1dh capcom register 14 cc14ir cc14ie cc14int 00'0078h 1eh capcom register 15 cc15ir cc15ie cc15int 00'007ch 1fh capcom register 16 cc16ir cc16ie cc16int 00'00c0h 30h capcom register 17 cc17ir cc17ie cc17int 00'00c4h 31h
ST10F167 19/61 note two x-peripheral nodes can accept interrupt requests from integrated x-bus peripherals. nodes where no x-peripherals are connected may be used to generate software controlled interrupt requests by setting the respective xpnir bit. capcom register 18 cc18ir cc18ie cc18int 00'00c8h 32h capcom register 19 cc19ir cc19ie cc19int 00'00cch 33h capcom register 20 cc20ir cc20ie cc20int 00'00d0h 34h capcom register 21 cc21ir cc21ie cc21int 00'00d4h 35h capcom register 22 cc22ir cc22ie cc22int 00'00d8h 36h capcom register 23 cc23ir cc23ie cc23int 00'00dch 37h capcom register 24 cc24ir cc24ie cc24int 00'00e0h 38h capcom register 25 cc25ir cc25ie cc25int 00'00e4h 39h capcom register 26 cc26ir cc26ie cc26int 00'00e8h 3ah capcom register 27 cc27ir cc27ie cc27int 00'00ech 3bh capcom register 28 cc28ir cc28ie cc28int 00'00e0h 3ch capcom register 29 cc29ir cc29ie cc29int 00'0110h 44h capcom register 30 cc30ir cc30ie cc30int 00'0114h 45h capcom register 31 cc31ir cc31ie cc31int 00'0118h 46h capcom timer 0 t0ir t0ie t0int 00'0080h 20h capcom timer 1 t1ir t1ie t1int 00'0084h 21h capcom timer 7 t7ir t7ie t7int 00'00f4h 3dh capcom timer 8 t8ir t8ie t8int 00'00f8h 3eh gpt1 timer 2 t2ir t2ie t2int 00'0088h 22h gpt1 timer 3 t3ir t3ie t3int 00'008ch 23h gpt1 timer 4 t4ir t4ie t4int 00'0090h 24h gpt2 timer 5 t5ir t5ie t5int 00'0094h 25h gpt2 timer 6 t6ir t6ie t6int 00'0098h 26h gpt2 caprel register crir crie crint 00'009ch 27h a/d conversion complete adcir adcie adcint 00'00a0h 28h a/d overrun error adeir adeie adeint 00'00a4h 29h asc0 transmit s0tir s0tie s0tint 00'00a8h 2ah asc0 transmit buffer s0tbir s0tbie s0tbint 00'011ch 47h asc0 receive s0rir s0rie s0rint 00'00ach 2bh asc0 error s0eir s0eie s0eint 00'00b0h 2ch ssc transmit sctir sctie sctint 00'00b4h 2dh ssc receive scrir scrie scrint 00'00b8h 2eh ssc error sceir sceie sceint 00'00bch 2fh pwm channel 0...3 pwmir pwmie pwmint 00'00fch 3fh can interface xp0ir xp0ie xp0int 00'0100h 40h x-peripheral node xp1ir xp1ie xp1int 00'0104h 41h x-peripheral node xp2ir xp2ie xp2int 00'0108h 42h pll unlock xp3ir xp3ie xp3int 00'010ch 43h table 5 : list of interrupt sources source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number viii - interrupt system (continued)
ST10F167 20/61 the ST10F167 identifies and to processes exceptions or error conditions that arise during run-time, `hardware traps'. hardware traps cause an immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag regis- ter (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any current program execution. in turn, hardware trap services can normally not be inter- rupted by standard or pec interrupts table 6 shows all of the possible exceptions or error conditions that can arise during run-time. table 6 : exceptions or error conditions that can arise during run time exception conditi on trap flag trap vector vector location trap number trap priority reset functions: hardware reset software reset watchdog timer overflow reset reset reset 00'0000h 00'0000h 00'0000h 00h 00h 00h iii iii iii class a hardware traps: non-maskable interrupt stack overflow stack underflow nmi stkof stkuf nmitrap stotrap stutrap 00'0008h 00'0010h 00'0018h 02h 04h 06h ii ii ii class b hardware traps: undefined opcode protected instruction fault illegal word operand access illegal instruction access illegal external bus access undopc prtflt illopa illina illbus btrap btrap btrap btrap btrap 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h 0ah 0ah 0ah 0ah 0ah i reserved [2ch 3ch] [0bh 0fh] software traps: trap instruction any [00'0000h 00'01fch] in steps of 4h any [00h 7fh] current cpu priority viii - interrupt system (continued)
ST10F167 21/61 ix - capture/compare (capcom) unit the capcom units support generation and con- trol of timing sequences on up to 32 channels. it has a maximum resolution of 400ns at 20mhz cpu clock. the capcom units are typically used to handle high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digital to analog (d/a) conversion, soft- ware timing, or time recording relative to external events. four 16-bit timers (t0/t1, t7/t8) with reload reg- isters, provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to several pre-scaled values of the internal system clock, or may be derived from an overflow/under- flow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. in addition, external count inputs for capcom timers t0 and t7 allow event scheduling for the capture/com- pare registers relative to external events. both of the two capture/compare register arrays contain 16 dual purpose capture/compare regis- ters, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, respectively), and programmed for capture or compare function. each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin (except for cc24...cc27) to indicate the occur- rence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is gener- ated. either a positive, a negative, or both a posi- tive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continu- ously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken, based on the selected compare mode (see table 7). the input frequencies f tx for tx are determined as a function of the cpu clocks. the formulas are detailed in the user manual. the timer input fre- quencies, resolution and periods which result from the selected pre-scaler option in txi when using a 25mhz cpu clock are listed in the table below. the numbers for the timer periods are based on a reload value of 0000 h . note that some numbers may be rounded to 3 significant figures (see table 8). table 7 : compare modes compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. table 8 : capcom timer input frequencies, resolution and periods f cpu = 25mhz timer inpu t selection txi 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b pre-scaler for f cpu 8 16 32 64 128 256 512 1024 input frequency 2.5mhz 1.25mhz 625khz 313khz 156khz 78.1khz 39.1khz 19.5khz resolution 400ns 800ns 1.60 m s 3.20 m s 6.40 m s 12.8 m s 25.6 m s51.2 m s period 26.2ms 52.4ms 105ms 210ms 419ms 839ms 1.68s 3.36s
ST10F167 22/61 x - general purpose timer (gpt) unit the gpt unit is a flexible multifunctional timer/ counter structure. it may be used for many different time-related tasks such as: event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. the gpt unit incorporates five 16-bit timers which are organized in two separate modules, gpt1 and gpt2. each timer, in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. x.1 - gpt1 each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of three basic modes of operation: timer , gated timer , and counter mode. in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable prescaler. counter mode allows a timer to be clocked in ref- erence to external events. pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. each timer has one associated port pin (txin) which are the gate or the clock input. table 9 gpt1 timer input frequencies, resolution and periods lists the timer input frequencies, resolution and periods for each pre-scaler option at 25mhz cpu clock. this also applies to the gated timer mode of t3 and to the auxiliary timers t2 and t4 in timer and gated timer mode (see table 9). the count direction (up/down) for each timer is pro- grammable by software or may be altered dynami- cally by an external signal on a port pin (txeud) to facilitate, for example, position tracking. timer t3 has output toggle latches (txotl) which changes state on each timer over-flow/underflow. the state of this latch may be output on port pins (txout) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 are captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the contents of t2 or t4, triggered, either by an external signal, or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention. x.2 - gpt2 the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is sup- ported by the output toggle latch (t6otl) of timer t6, which changes its state on each timer over- flow/underflow. the state of this latch may be used to clock timer t5, or it may be output on a port pin (t6out). the overflows/underflows of timer t6 can additionally be used to clock the capcom timers t0 or t1, and to cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture proce- dure. this allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. table 9 : gpt1 timer input frequencies, resolution and periods f cpu = 25mhz timer input selection t2i / t3i / t4i 000b 001b 010b 011b 100b 101b 110b 111b pre scaler 8 16 32 64 128 256 512 1024 input frequency 2.5mhz 1.25mhz 625khz 313khz 156khz 78.1khz 39.1khz 19.5khz resolution 400ns 800ns 1.60 m s 3.20 m s 6.40 m s 12.8 m s 25.6 m s 51.2 m s period 26.2ms 52.4ms 105ms 210ms 419ms 839ms 1.68s 3.36s
ST10F167 23/61 table 10 gpt2 timer input frequencies, resolution and period lists the timer input frequencies, reso- lution and periods for each pre-scaler option at 25mhz cpu clock. this also applies to the gated timer mode of t6 and to the auxiliary timer t5 in timer and gated timer mode. table 10 : gpt2 timer input frequencies, resolution and period f cpu = 25mhz timer input selection t5i / t6i 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b pre-scaler factor 4 8 16 32 64 128 256 512 input frequency 5mhz 2.5mhz 1.25mhz 625khz 313khz 156khz 78.1khz 39.1khz resolution 200ns 400ns 800ns 1.60 m s 3.20 m s 6.40 m s 12.8 m s 25.6 m s period 13.11ms 26.2ms 52.4ms 105ms 210ms 419ms 839ms 1.68s figure 7 : block diagram of gpt1 2 n n=3...10 2 n n=3...10 2 n n=3...10 t2eud t2in cpu clock cpu clock cpu clock t3eud t4in t3in t4eud t2 mode control t3 mode control t4 mode control gpt1 timer t2 gpt1 timer t3 gpt1 timer t4 t3otl reload capture u/d u/d reload capture interrupt request interrupt request interrupt request t3out u/d x - general purpose timer (gpt) unit (continued)
ST10F167 24/61 figure 8 : block diagram of gpt2 2n n=2...9 2n n=2...9 t5eud t5in cpu clock cpu clock t6in t6eud t5 mode control t6 mode gpt2 timer t5 gpt2 timer t6 u/d interrupt request u/d gpt2 caprel t60tl toggle ff t6out capin reload interrupt request to capcom timers capture clear interrupt request x - general purpose timer (gpt) unit (continued)
ST10F167 25/61 xi - pwm module the pulse width modulation unit can generate up to four pwm output signals using edge-aligned or centre-aligned pwm. in addition, the pwm mod- ule can generate pwm burst signals and single shot outputs. table 11 shows the pwm frequen- cies for different resolutions. the level of the out- put signals is selectable and the pwm module can generate interrupt requests. table 11 : pwm unit frequencies and resolution at 25mhz cpu clock mode 0 resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 50ns 78.13khz 19.53khz 4.883khz 1.221khz 0.305khz cpu clock/64 3.2ns 1.221khz 305.2hz 76.29hz 19.07hz 4.768hz mode 1 resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 50ns 39.06khz 9.766khz 2.441khz 610.4hz 152.6hz cpu clock/64 3.2ns 610.4hz 152.6 hz 38.15hz 9.537hz 2.38hz figure 9 : block diagram of pwm module ppx period register comparator ptx 16-bit up/down counter shadow register pwx pulse width register input run control clock 1 clock 2 comparator * * * up/down/ clear control match output control match write control * user read-& writeable enable poutx
ST10F167 26/61 xii - parallel ports the ST10F167 provides up to 111 i/o lines which are organized into eight input/output ports and one input port. all port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as input or output via direction reg- isters. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the output drivers of three i/o ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. during the internal reset, all port pins are configured as inputs. the input threshold of port 2, port 3, port 7 and port 8 is selectable (ttl-or cmos-like). the spe- cial cmos-like input threshold reduces noise sen- sitivity due to the input hysteresis. the input threshold may be selected individually for each byte of the respective ports. all port lines have associated programmable alter- nate input or output functions. port0 and port1 may be used as address and data lines when accessing external memory, while port 4 outputs the additional segment address bits a23/19/ 17...a16 in systems where segmentation is enabled to access more than 64k byte of memory. port 2, port 8 and port 7 are associated with the capture inputs or compare outputs of the cap- com units and/or with the outputs of the pwm module. port 6 provides optional bus arbitration signals (breq, hlda, hold) and chip select signals. port 3 includes alternate functions of tim- ers, serial interfaces, the optional bus control sig- nal bhe and the system clock output (clkout). port 5 is used for the analog input channels to the a/d converter or timer control signals. all port lines that are not used for these alternate functions may be used as general purpose i/o lines. xiii - a/d converter a 10-bit a/d converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip for analog signal measure- ment. it uses a successive approximation method. the sample time (for loading the capacitors) and conversion time is programmable and can be modified for the external circuitry. overrun error detection/protection is provided through the conversion result register (addat). when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, either an interrupt request is generated, or the next conversion is sus- pended, until the previous result has been read. for applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converter of the ST10F167 supports four different conversion modes. single channel conversion mode: the analog level on a specified channel is sampled once and converted to a digital result. single channel continuous mode: the analog level on a specified channel is repeatedly sam- pled and converted without software intervention. auto scan mode: the analog levels on a pre- specified number of channels are sequentially sampled and converted. auto scan continuous mode: the number of pre- specified channels is repeatedly sampled and converted. in addition, channel injection mode injects a chan- nel into a running sequence without disturbing the sequence. the peripheral event controller stores the conversion results in memory without entering and exiting interrupt routines for each data transfer. table 12 shows the adc unit conversion clock, sample clock and complete conversion times. after each reset and also during normal operation, the adc automatically performs calibration cycles. this automatic self-calibration constantly adjusts the converter to the changing operating conditions (e.g. temperature) and compensates for any process variations. these calibration cycles are part of the conversion cycle and do not affect the normal operation of the a/d converter. table 12 : adc sample clock and conversion time adctc conversion clock tcc adstc sample clock tsc complete conversion 00 0.6 m s 00 0.6 m s 9.7 m s 01 reserved 01 reserved 10 2.4 m s 10 9.6 m s 52.9 m s 11 1.2 m s 11 9.6 m s 36.1 m s
ST10F167 27/61 xiv - serial channels serial communication with other microcontrollers, processors, terminals or external peripheral compo- nents is provided by two serial interfaces. an asyn- chronous/synchronous serial channel (asc0) and a high-speed synchronous serial channel (ssc). xiv.1 - asco asc0 supports full-duplex asynchronous commu- nication up to 625 kbaud and half-duplex syn- chronous communication up to 2.5 mbaud @ 20mhz system clock. the ssc allows half duplex synchronous commu- nication up to 5 mbaud @ 20mhz system clock. for asynchronous operation, the baud rate gener- ator provides a clock with 16 times the rate of the established baud rate. the table below lists vari- ous commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate (see table 14). for synchronous operation, the baud rate genera- tor provides a clock with 4 times the rate of the established baud rate. xiv.2 - high speed synchronous serial channel (ssc) the high-speed synchronous serial interface ssc provides flexible high-speed serial communi- cation between the ST10F167 and other microcon- trollers, microprocessors or external peripherals. the ssc supports full-duplex and half-duplex synchronous communication; the serial clock sig- nal can be generated by the ssc itself (master mode) or be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data is double-buff- ered. a 16-bit baud rate generator provides the ssc with a separate serial clock signal. the serial channel ssc has its own dedicated 16-bit baud rate generator with 16-bit reload capa- bility, allowing baud rate generation independent from the timers. sscbr is the dual-function baud rate generator/ reload register. table 13 lists some possible baud rates against the required reload values and the resulting bit times for a 25mhz cpu clock. note the deviation errors given in the table above are rounded. using a baudrate crystal will provide correct baudrates without deviation errors. table 13 : synchronous baud rate and reload values baud rate bit time reload value reserved use a reload value > 0. --- 0000 h 5 mbaud 200ns 0001 h 3.3 mbaud 303ns 0002 h 2.5 mbaud 400ns 0003 h 2 mbaud 500ns 0004 h 1 mbaud 1 m s 0009 h 100 kbaud 10 m s 0063 h 10 kbaud 100 m s 03e7 h 1 kbaud 1ms 270f h 152.6 baud 6.6ms ffff h table 14 : commonly used baud rates by reload value and deviation errors s0brs = `0', f cpu = 25mhz s0brs = `1', f cpu = 25mhz baud rate (baud) deviation error reload value baud rate (baud) deviation error reload value 625000 0.0% 0000 h 416666 0.0% 0000 h 56000 +1.5% / -7.0% 000a h / 000b h 56000 +6.3% / -7.0% 0006 h / 0007 h 38400 +1.7% / -4.3% 000f h / 0010 h 38400 +8.5% / -1.4% 0009 h / 000a h 19200 +1.7% / -1.4% 001f h / 0020 h 19200 +3.3% / -1.4% 0014 h / 0015 h 9600 +0.2% / -1.4% 0040 h / 0041 h 9600 +0.9% / -1.4% 002a h / 002b h 4800 +0.2% / -0.6% 0081 h / 0082 h 4800 +0.9% / -0.2% 0055 h / 0056 h 2400 +0.2% / -0.2% 0103 h / 0104 h 2400 +0.4% / -0.2% 00ac h /00ad h 1200 +0.2% / -0.0% 0207 h / 0208 h 1200 +0.1% / -0.2% 015a h / 015b h 600 +0.1% / -0.0% 0410 h / 0411 h 600 +0.1% / -0.1% 02b5 h / 02b6 h 76 +0.4% / 0.4% 1fff h / 1fff h 75 +0.0% / 0.0% 15b2 h /15b3 h 50 +1.7% / 1.7% 1fff h / 1fff h
ST10F167 28/61 xv - can module the integrated can-module performs the autono- mous transmission and reception of can frames in accordance with the can specification v2.0 part b (active). the on-chip can-module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. the module provides full can functionality for up to 15 message objects. message object 15 may be configured for basic can functionality. both modes provide separate masks for acceptance fil- tering allowing a number of identifiers in full can mode to be accepted and also allows to disre- garded a number of identifiers in basic can mode to be disregarded. all message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 byte. the bit timing is derived from the xclk and is pro- grammable up to a data rate of 1 mbaud. the can-module uses two pins to interface to a bus transceiver. xvi - watchdog timer the watchdog timer is a fail-safe mechanism which prevents the microcontroller from malfunc- tioning for long periods of time. the watchdog timer is always enabled after a reset of the chip and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. therefore, the chip start-up procedure is always monitored. the software must be designed to service the watch- dog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and gener- ates an internal hardware reset. it pulls the rstout pin low in order to allow external hard- ware components to be reset. the watchdog timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. the high byte of the watchdog timer register can be set to a pre-specified reload value (stored in wdtrel. each time it is serviced by the appli- cation software, the high byte of the watchdog timer is reloaded. table 15 shows the watchdog timer range for 25mhz cpu clock. some numbers are rounded to 3 significant digits. note for security, rewrite wdtc on each time before the watchdog timer is serviced. table 15 : watchdog timer range reload value in wdtrel prescaler for f cpu 2 (wdtin = `0') 128 (wdtin = `1') ff h 25.6 m s 1.64 ms 00 h 6.55 ms 419 ms
ST10F167 29/61 xvii - instruction set the table below lists the instruction set of the ST10F167. more detailed information such as address modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the ast10 family programming manualo . table 16 : instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand. with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 j(n)b jump relative if direct bit is (not) set 4
ST10F167 30/61 xviii - bootstrap loader the built-in bootstrap loader of the ST10F167 pro- vides a mechanism to load the startup program through the serial interface after reset. the ST10F167 enters bsl mode when pin p0l.4 is sampled low at the end of a hardware reset. in this case the built-in bootstrap loader is acti- vated independent of the selected bus mode. the bootstrap loader code is stored in a special boot-rom. no part of the standard mask rom or flash mem- ory area is required. the identification byte is returned in c5 h . jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bit if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack & call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word oper- and 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (assumes nmi-pin low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 16 : instruction set summary mnemonic description bytes xvii - instruction set (continued)
ST10F167 31/61 xix - special function registers table 17 lists all ST10F167 sfrs in alphabetical order. bit-addressable sfrs are marked with the letter a b o in column anameo. sfrs within the extended sfr-space (esfrs) are marked with the letter a e o in column aphysical addresso. an sfr can be specified via its individual mne- monic name. depending on the selected address- ing mode, an sfr can be accessed via its physical address (using the data page pointers), or via its short 8-bit address (without using the data page pointers). table 17 : special function registers listed by name name physical address 8-bit address description reset value adcic b ff98h cch a/d converter end of conversion interrupt cont register 0000h adcon b ffa0h d0h a/d converter control register 0000h addat fea0h 50h a/d converter result register 0000h addat2 f0a0h e 50h a/d converter 2 result register 0000h addrsel1 fe18h 0ch address select register 1 0000h addrsel2 fe1ah 0dh address select register 2 0000h addrsel3 fe1ch 0eh address select register 3 0000h addrsel4 fe1eh 0fh address select register 4 0000h adeic b ff9ah cdh a/d converter overrun error interrupt control register 0000h buscon0 b ff0ch 86h bus configuration register 0 0xx0h buscon1 b ff14h 8ah bus configuration register 1 0000h buscon2 b ff16h 8bh bus configuration register 2 0000h buscon3 b ff18h 8ch bus configuration register 3 0000h buscon4 b ff1ah 8dh bus configuration register 4 0000h caprel fe4ah 25h gpt2 capture/reload register 0000h cc0 fe80h 40h capcom register 0 0000h cc0ic b ff78h bch capcom register 0 interrupt control register 0000h cc1 fe82h 41h capcom register 1 0000h cc1ic b ff7ah bdh capcom register 1 interrupt control register 0000h cc2 fe84h 42h capcom register 2 0000h cc2ic b ff7ch beh capcom register 2 interrupt control register 0000h cc3 fe86h 43h capcom register 3 0000h cc3ic b ff7eh bfh capcom register 3 interrupt control register 0000h cc4 fe88h 44h capcom register 4 0000h cc4ic b ff80h c0h capcom register 4 interrupt control register 0000h cc5 fe8ah 45h capcom register 5 0000h cc5ic b ff82h c1h capcom register 5 interrupt control register 0000h cc6 fe8ch 46h capcom register 6 0000h cc6ic b ff84h c2h capcom register 6 interrupt control register 0000h cc7 fe8eh 47h capcom register 7 0000h cc7ic b ff86h c3h capcom register 7 interrupt control register 0000h
ST10F167 32/61 cc8 fe90h 48h capcom register 8 0000h cc8ic b ff88h c4h capcom register 8 interrupt control register 0000h cc9 fe92h 49h capcom register 9 0000h cc9ic b ff8ah c5h capcom register 9 interrupt control register 0000h cc10 fe94h 4ah capcom register 10 0000h cc10ic b ff8ch c6h capcom register 10 interrupt control register 0000h cc11 fe96h 4bh capcom register 11 0000h cc11ic b ff8eh c7h capcom register 11 interrupt control register 0000h cc12 fe98h 4ch capcom register 12 0000h cc12ic b ff90h c8h capcom register 12 interrupt control register 0000h cc13 fe9ah 4dh capcom register 13 0000h cc13ic b ff92h c9h capcom register 13 interrupt control register 0000h cc14 fe9ch 4eh capcom register 14 0000h cc14ic b ff94h cah capcom register 14 interrupt control register 0000h cc15 fe9eh 4fh capcom register 15 0000h cc15ic b ff96h cbh capcom register 15 interrupt control register 0000h cc16 fe60h 30h capcom register 16 0000h cc16ic b f160h e b0h capcom register 16 interrupt control register 0000h cc17 fe62h 31h capcom register 17 0000h cc17ic b f162h e b1h capcom register 17 interrupt control register 0000h cc18 fe64h 32h capcom register 18 0000h cc18ic b f164h e b2h capcom register 18 interrupt control register 0000h cc19 fe66h 33h capcom register 19 0000h cc19ic b f166h e b3h capcom register 19 interrupt control register 0000h cc20 fe68h 34h capcom register 20 0000h cc20ic b f168h e b4h capcom register 20 interrupt control register 0000h cc21 fe6ah 35h capcom register 21 0000h cc21ic b f16ah e b5h capcom register 21 interrupt control register 0000h cc22 fe6ch 36h capcom register 22 0000h cc22ic b f16ch e b6h capcom register 22 interrupt control register 0000h cc23 fe6eh 37h capcom register 23 0000h cc23ic b f16eh e b7h capcom register 23 interrupt control register 0000h cc24 fe70h 38h capcom register 24 0000h cc24ic b f170h e b8h capcom register 24 interrupt control register 0000h cc25 fe72h 39h capcom register 25 0000h cc25ic b f172h e b9h capcom register 25 interrupt control register 0000h table 17 : special function registers listed by name (continued) name physical address 8-bit address description reset value xix - special function registers (continued)
ST10F167 33/61 cc26 fe74h 3ah capcom register 26 0000h cc26ic b f174h e bah capcom register 26 interrupt control register 0000h cc27 fe76h 3bh capcom register 27 0000h cc27ic b f176h e bbh capcom register 27 interrupt control register 0000h cc28 fe78h 3ch capcom register 28 0000h cc28ic b f178h e bch capcom register 28 interrupt control register 0000h cc29 fe7ah 3dh capcom register 29 0000h cc29ic b f184h e c2h capcom register 29 interrupt control register 0000h cc30 fe7ch 3eh capcom register 30 0000h cc30ic b f18ch e c6h capcom register 30 interrupt control register 0000h cc31 fe7eh 3fh capcom register 31 0000h cc31ic b f194h e cah capcom register 31 interrupt control register 0000h ccm0 b ff52h a9h capcom mode control register 0 0000h ccm1 b ff54h aah capcom mode control register 1 0000h ccm2 b ff56h abh capcom mode control register 2 0000h ccm3 b ff58h ach capcom mode control register 3 0000h ccm4 b ff22h 91h capcom mode control register 4 0000h ccm5 b ff24h 92h capcom mode control register 5 0000h ccm6 b ff26h 93h capcom mode control register 6 0000h ccm7 b ff28h 94h capcom mode control register 7 0000h cp fe10h 08h cpu context pointer register fc00h cric b ff6ah b5h gpt2 caprel interrupt control register 0000h csp fe08h 04h cpu code segment pointer register (read only) 0000h dp0l b f100h e 80h p0l direction control register 00h dp0h b f102h e 81h p0h direction control register 00h dp1l b f104h e 82h p1l direction control register 00h dp1h b f106h e 83h p1h direction control register 00h dp2 b ffc2h e1h port 2 direction control register 0000h dp3 b ffc6h e3h port 3 direction control register 0000h dp4 b ffcah e5h port 4 direction control register 00h dp6 b ffceh e7h port 6 direction control register 00h dp7 b ffd2h e9h port 7 direction control register 00h dp8 b ffd6h ebh port 8 direction control register 00h dpp0 fe00h 00h cpu data page pointer 0 register (10 bits) 0000h dpp1 fe02h 01h cpu data page pointer 1 register (10 bits) 0001h dpp2 fe04h 02h cpu data page pointer 2 register (10 bits) 0002h table 17 : special function registers listed by name (continued) name physical address 8-bit address description reset value xix - special function registers (continued)
ST10F167 34/61 dpp3 fe06h 03h cpu data page pointer 3 register (10 bits) 0003h exicon b f1c0h e e0h external interrupt control register 0000h mdc b ff0eh 87h cpu multiply divide control register 0000h mdh fe0ch 06h cpu multiply divide register high word 0000h mdl fe0eh 07h cpu multiply divide register low word 0000h odp2 b f1c2h e e1h port 2 open drain control register 0000h odp3 b f1c6h e e3h port 3 open drain control register 0000h odp6 b f1ceh e e7h port 6 open drain control register 00h odp7 b f1d2h e e9h port 7 open drain control register 00h odp8 b f1d6h e ebh port 8 open drain control register 00h ones ff1eh 8fh constant value 1's register (read only) ffffh p0l b ff00h 80h port 0 low register (lower half of port0) 00h p0h b ff02h 81h port 0 high register (upper half of port0) 00h p1l b ff04h 82h port 1 low register (lower half of port1) 00h p1h b ff06h 83h port 1 high register (upper half of port1) 00h p2 b ffc0h e0h port 2 register 0000h p3 b ffc4h e2h port 3 register 0000h p4 b ffc8h e4h port 4 register (8 bits) 00h p5 b ffa2h d1h port 5 register (read only) xxxxh p6 b ffcch e6h port 6 register (8 bits) 00h p7 b ffd0h e8h port 7 register (8 bits) 00h p8 b ffd4h eah port 8 register (8 bits) 00h pecc0 fec0h 60h pec channel 0 control register 0000h pecc1 fec2h 61h pec channel 1 control register 0000h pecc2 fec4h 62h pec channel 2 control register 0000h pecc3 fec6h 63h pec channel 3 control register 0000h pecc4 fec8h 64h pec channel 4 control register 0000h pecc5 fecah 65h pec channel 5 control register 0000h pecc6 fecch 66h pec channel 6 control register 0000h pecc7 feceh 67h pec channel 7 control register 0000h picon f1c4h e e2h port input threshold control register 0000h pp0 f038h e 1ch pwm module period register 0 0000h pp1 f03ah e 1dh pwm module period register 1 0000h pp2 f03ch e 1eh pwm module period register 2 0000h pp3 f03eh e 1fh pwm module period register 3 0000h psw b ff10h 88h cpu program status word 0000h table 17 : special function registers listed by name (continued) name physical address 8-bit address description reset value xix - special function registers (continued)
ST10F167 35/61 pt0 f030h e 18h pwm module up/down counter 0 0000h pt1 f032h e 19h pwm module up/down counter 1 0000h pt2 f034h e 1ah pwm module up/down counter 2 0000h pt3 f036h e 1bh pwm module up/down counter 3 0000h pw0 fe30h 18h pwm module pulse width register 0 0000h pw1 fe32h 19h pwm module pulse width register 1 0000h pw2 fe34h 1ah pwm module pulse width register 2 0000h pw3 fe36h 1bh pwm module pulse width register 3 0000h pwmcon0 b ff30h 98h pwm module control register 0 0000h pwmcon1 b ff32h 99h pwm module control register 1 0000h pwmic b f17eh e bfh pwm module interrupt control register 0000h rp0h b f108h e 84h system startup configuration register (read only) xxh s0bg feb4h 5ah serial channel 0 baud rate generator reload register 0000h s0con b ffb0h d8h serial channel 0 control register 0000h s0eic b ff70h b8h serial channel 0 error interrupt control register 0000h s0rbuf feb2h 59h serial channel 0 receive buffer register (read only) xxh s0ric b ff6eh b7h serial channel 0 receive interrupt control register 0000h s0tbic b f19ch e ceh serial channel 0 transmit buffer interrupt control register 0000h s0tbuf feb0h 58h serial channel 0 transmit buffer register (write only) 00h s0tic b ff6ch b6h serial channel 0 transmit interrupt control register 0000h sp fe12h 09h cpu system stack pointer register fc00h sscbr f0b4h e 5ah ssc baudrate register 0000h ssccon b ffb2h d9h ssc control register 0000h ssceic b ff76h bbh ssc error interrupt control register 0000h sscrb f0b2h e 59h ssc receive buffer (read only) xxxxh sscric b ff74h bah ssc receive interrupt control register 0000h ssctb f0b0h e 58h ssc transmit buffer (write only) 0000h ssctic b ff72h b9h ssc transmit interrupt control register 0000h stkov fe14h 0ah cpu stack overflow pointer register fa00h stkun fe16h 0bh cpu stack underflow pointer register fc00h syscon b ff12h 89h cpu system configuration register 0xx0h 1 t0 fe50h 28h capcom timer 0 register 0000h t01con b ff50h a8h capcom timer 0 and timer 1 control register 0000h t0ic b ff9ch ceh capcom timer 0 interrupt control register 0000h t0rel fe54h 2ah capcom timer 0 reload register 0000h t1 fe52h 29h capcom timer 1 register 0000h table 17 : special function registers listed by name (continued) name physical address 8-bit address description reset value xix - special function registers (continued)
ST10F167 36/61 notes 1. the system configuration is selected during reset. 2. bit wdtr indicates a watchdog timer triggered reset. 3. the interrupt control registers xpnic, control interrupt requests from integrated x-bus peripherals. nodes, where no x-peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective xpnir bit. t1ic b ff9eh cfh capcom timer 1 interrupt control register 0000h t1rel fe56h 2bh capcom timer 1 reload register 0000h t2 fe40h 20h gpt1 timer 2 register 0000h t2con b ff40h a0h gpt1 timer 2 control register 0000h t2ic b ff60h b0h gpt1 timer 2 interrupt control register 0000h t3 fe42h 21h gpt1 timer 3 register 0000h t3con b ff42h a1h gpt1 timer 3 control register 0000h t3ic b ff62h b1h gpt1 timer 3 interrupt control register 0000h t4 fe44h 22h gpt1 timer 4 register 0000h t4con b ff44h a2h gpt1 timer 4 control register 0000h t4ic b ff64h b2h gpt1 timer 4 interrupt control register 0000h t5 fe46h 23h gpt2 timer 5 register 0000h t5con b ff46h a3h gpt2 timer 5 control register 0000h t5ic b ff66h b3h gpt2 timer 5 interrupt control register 0000h t6 fe48h 24h gpt2 timer 6 register 0000h t6con b ff48h a4h gpt2 timer 6 control register 0000h t6ic b ff68h b4h gpt2 timer 6 interrupt control register 0000h t7 f050h e 28h capcom timer 7 register 0000h t78con b ff20h 90h capcom timer 7 and 8 control register 0000h t7ic b f17ah e beh capcom timer 7 interrupt control register 0000h t7rel f054h e 2ah capcom timer 7 reload register 0000h t8 f052h e 29h capcom timer 8 register 0000h t8ic b f17ch e bfh capcom timer 8 interrupt control register 0000h t8rel f056h e 2bh capcom timer 8 reload register 0000h tfr b ffach d6h trap flag register 0000h wdt feaeh 57h watchdog timer register (read only) 0000h wdtcon ffaeh d7h watchdog timer control register 000xh 2 xp0ic b f186h e c3h can module interrupt control register 0000h xp1ic b f18eh e c7h x-peripheral 1 interrupt control register 0000h xp2ic b f196h e cbh x-peripheral 2 interrupt control register 0000h xp3ic b f19eh e cfh pll interrupt control register 0000h zeros b ff1ch 8eh constant value 0's register (read only) 0000h table 17 : special function registers listed by name (continued) name physical address 8-bit address description reset value xix - special function registers (continued)
ST10F167 37/61 xx - electrical characteristics xx.1 - absolute maximum ratings ambient temperature under bias (ta) : ST10F167 40 to +85 c. storage temperature (tst) : 65 to +150 c. voltage on v dd pins with respect to ground (v ss ) : 0.5 to +6.5 v. voltage on any pin with respect to ground (v ss ): 0.3 to v dd +0.3 v. input current on any pin during overload condition : 10 to +10 ma. absolute sum of all input currents during over- load condition : |100 ma|. power dissipation : 1.5 w. note stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in ST10F167 and its demands on the system. where the ST10F167 logic provides signals with their respective timing characteristics, the symbol acco for controller characteristics is included in the asymbolo column. where the external system must provide signals with their respective timing characteristics to the ST10F167, the symbol asro for system require- ment is included in the asymbolo column. xx.3 - dc characteristics v dd =5v 5%, v ss =0,f cpu = 20mhz, reset active, t a = -40 to + 85 c table 18 : dc characteristics parameter symbol limit values unit test conditio n min. max. input low voltage (ttl) v il sr 0.5 0.2 v dd 0.1 v input low voltage (special threshold) v ils sr 0.5 2.0 v input high voltage, all except rstin and xtal1 (ttl) v ih sr 0.2 v dd + 0.9 v dd + 0.5 v input high voltage rstin v ih1 sr 0.6 v dd v dd + 0.5 v input high voltage xtal1 v ih2 sr 0.7 v dd v dd + 0.5 v input high voltage (special threshold) v ihs sr 0.8 v dd - 0.2 v dd + 0.5 v input hysteresis (special threshold) hys 400 - mv output low voltage (port0, port1, port 4, ale, rd, wr, bhe, clkout, rstout) v ol cc 0.45 v i ol = 2.4 ma output low voltage (all other outputs) v ol1 cc 0.45 v i ol1 = 1.6 ma output high voltage (port0, port1, port 4, ale, rd, wr, bhe, clkout, rstout) v oh cc 0.9 v dd 2.4 vi oh = 500 m a i oh = 2.4 ma output high voltage 1 (all other outputs) v oh1 cc 0.9 v dd 2.4 vi oh = 250 m a i oh = 1.6 ma input leakage current (port 5) i oz1 cc 1 m a 0.45v < v in ST10F167 38/61 notes 1. this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 2. the maximum current may be drawn while the respective signal line remains inactive. 3. the minimum current must be drawn in order to drive the respective signal line active. 4. this specification is only valid during reset, or during hold- or adapt-mode. port 6 pins are only affected if they are used for cs output and the open drain function is not enabled. 5. not 100% tested, guaranteed by design characterization. 6. the supply current is a function of the operating frequency. this dependency is illustrated in the figure below. these parameters are tested at v ddmax and 20 mhz cpu clock with all outputs disconnected and all inputs at v il or v ih . 7. this parameter is tested including leakage currents. all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v dd 0.1 v to v dd ,v ref = 0 v, all outputs (including pins configured as outputs) disconnected. 8. overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov >v dd +0.5v or v ov ST10F167 39/61 xx - electrical characteristics (continued) xx.4 - a/d converter characteristics v dd =5v 5%, v ss =0v,t a = -40 to +85 c 4.0 v < v aref ST10F167 40/61 4. this parameter depends on the adc control logic. it is not a real maximum value, but rather a fixum. 5. tue is tested at v aref =5.0v, v agnd =0v, v dd =4.9v. it is guaranteed by design characterization for all other voltages within the defined voltage range. the specified tue is guaranteed only if an overload condition (see iov specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma. during the reset calibration sequence the maximum tue may be 4 lsb. 6. during the conversion the adc's capacitance must be repeatedly charged or discharged. the internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within t cc . the maximum internal resistance results from the programmed conversion timing. 7. not 100% tested, guaranteed by design characterization. sample time and conversion time of the ST10F167's adc are programmable. the table below shows the timing calculations. xx.5 - ac characteristics xx.5.1 - test waveforms table 20 : adc timing calculations adcon. 15|14 (adctc) conversion clock t cc adcon. 13|12 (adstc) sample clock t sc 00 tcl * 24 00 t cc 01 reserved, do not use 01 t cc *2 10 tcl * 96 10 t cc *4 11 tcl * 48 11 t cc *8 figure 11 : input output waveforms figure 12 : float waveforms 2.4v 0.45v test points 0.2v dd +0.9 0.2v dd +0.9 0.2v dd -0.1 0.2v dd -0.1 ac inputs during testing are driven at 2.4 v for a logic `1' and 0.4 v for a logic `0'. timing measurements are made at vih min for a logic `1' and vil max for a logic `0'. timing reference points vload +0.1v vload -0.1v voh -0.1v vol +0.1v vload vol voh for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs,butbegins to floatwhen a100 mv change fromthe loaded v oh /v ol leveloccurs (i oh /i ol = 20 ma). xx - electrical characteristics (continued)
ST10F167 41/61 xx.5.2 - definition of internal timing the internal operation of the ST10F167 is con- trolled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (e.g. pipe- line) or external (e.g. bus cycles) operations. the specification of the external timing (ac char- acteristics) therefore depends on the time between two consecutive edges of the cpu clock, called atclo (see table 23). the cpu clock signal can be generated via differ- ent mechanisms. the duration of tcl and its variation (and also the derived external timing) depends on the mecha- nism used to generate f cpu . this influence must be taken into consideration when calculating the timings for the ST10F167 (see figure 13). xx.5.3 - direct drive when pin p0.15 (p0h.7) is low (`0') during reset the on-chip phase locked loop is disabled and the cpu clock is directly driven from the oscillator with the input clock signal. the frequency of f cpu directly follows the fre- quency of f xtal so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f xtal . the timings listed below that refer to tcl there- fore must be calculated using the minimum tcl that is possible under the respective circum- stances. this minimum value can be calculated via the fol- lowing formula: for two consecutive tcl the deviation caused by the duty cycle of f xtal is compensated so the duration of 2tcl is always 1/f xtal . the minimum value tcl min therefore has to be used only once for timings that require an odd number of tcl (1,3,...). timings that require an even number of tcls (2,4,...) may use the formula: 2tcl = 1/f xtal. the address float timings in multiplexed bus mode (t 11 and t 45 ) use the maximum duration of tcl (tcl max = 1/f xtal *dc max ) instead of tcl min . xx.5.4 - phase locked loop when pin p0.15 (p0h.7) is high (`1') during reset the on-chip phase locked loop is enabled and pro- vides the cpu clock. the pll multiplies the input frequency by 4 (i.e. f cpu =f xtal * 4). with every fourth transition of f xtal the pll circuit synchro- nizes the cpu clock to the input clock. this syn- chronization is done smoothly, i.e. the cpu clock frequency does not change abruptly. due to this adaptation to the input clock the fre- quency of f cpu is constantly adjusted so it is locked to f xtal . the slight variation causes a jitter of f cpu which also effects the duration of individ- ual tcls. the timings listed in the ac characteristics that refer to tcl therefore must be calculated using the minimum tcl that is possible under the respective circumstances.. tcl min 1 f M xtal *dc min = dc duty cycle = figure 13 : generation mechanisms for the cpu clock tcl tcl tcl tcl f cpu f xtal f cpu f xtal phase locked loop operation direct clock drive xx - electrical characteristics (continued)
ST10F167 42/61 the actual minimum value for tcl depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so that it remains locked to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one tcl is lower than for one single tcl (see formula and figure below). for a period of n * tcl the minimum value is computed using the corresponding deviation d n : where n = number of consecutive tcls and 1 < n < 40. so for a period of 3 tcls (i.e. n = 3): this is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. xx.5.5 - external clock drive xtal1 v dd =5v 5%, v ss =0v,t a = -40 to +85 c note 1. theoretical minimum. the real minimum value depends on the duty cycle of the input clock signal. tcl min tcl nom * 1d n 100 M ) ( = d n 4 n15 ) % [] M ( = d 3 4315 M = 3.8% = tcl min tcl nom 1 3.8 100 M () = tcl nom 0.962 = 24.1 nsec@f cpu 20 mhz = () figure 14 : approximated maximum pll jitter this approximated formula is valid for 1 < n < 40 and 10mhz < f cpu < 20mhz. 32 16 8 4 2 1 2 3 4 max.jitter [%] n table 21 : external clock drive xtal1 parameter symbol direct drive 1:1 pll 1:4 unit min. max. min. max. oscillator period t osc sr 50 1 1000 200 333 ns high time t 1 sr 25 6 ns low time t 2 sr 25 6 ns rise time t 3 sr1010ns fall time t 4 sr1010ns xx - electrical characteristics (continued)
ST10F167 43/61 xx - electrical characteristics (continued) xx.5.6 - memory cycle variables the timing tables below use three variables which are derived from the busconx registers and repre- sent the special characteristics of the programmed memory cycle. the following table describes how these variables are to be computed. xx.5.7 - multiplexed bus v dd =5v 5%,v ss = 0 v, t a = -40 to +85 c c l (for port0, port1, port 4, ale, rd, wr, bhe, clkout) = 100 pf, c l (for port 6, cs) = 100 pf ale cycle time = 6 tcl + 2t a +t c +t f (150 ns at 20-mhz cpu clock without waitstates) figure 15 : external clock drive xtal1 table 22 : memory cycle variables description symbol values ale extension t a tcl * memory cycle time waitstates t c 2tcl * (15 - ) memory tristate time t f 2tcl * (1 - ) table 23 : multiplexed bus characteristics parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. ale high time t 5 cc 15 + t a tcl - 10 + t a ns address setup to ale t 6 cc 0 + t a tcl - 25 + t a ns address hold after ale t 7 cc 15 + t a tcl - 10 + t a ns ale falling edge to rd, wr (with rw-delay) t 8 cc 15 + t a tcl - 10 + t a ns ale falling edge to rd, wr (no rw-delay) t 9 cc -10 + t a -10 + t a ns address float after rd, wr (with rw-delay) t 10 cc 5 5 ns address float after rd, wr (no rw-delay) t 11 cc 30 tcl + 5 ns rd, wr low time (with rw-delay) t 12 cc 25 + t c 2tcl - 25 + t c ns rd, wr low time (no rw-delay) t 13 cc 65 + t c 3tcl - 10 + t c ns rd to valid data in (with rw-delay) t 14 sr 5 + t c 2tcl - 45 + t c ns t 1 t 3 t 4 v il t 2 t osc v ih2
ST10F167 44/61 rd to valid data in (no rw-delay) t 15 sr 55 + t c 3tcl - 20 + t c ns ale low to valid data in t 16 sr 40 + t a +t c 3tcl - 35 +t a +t c ns address to valid data in t 17 sr 60 + 2t a +t c 4tcl - 40 +2t a +t c ns data hold after rd rising edge t 18 sr 0 0 ns data float after rd t 19 sr 35 + t f 2tcl-15+t f ns data valid to wr t 22 sr 15 + t c 2tcl - 35 + t c ns data hold after wr t 23 cc 35 + t f 2tcl-15+t f ns ale rising edge after rd, wr t 25 cc 35 + t f 2tcl-15+t f ns address hold after rd, wr t 27 cc 35 + t f 2tcl-15+t f ns ale falling edge to cs t 38 cc -5 - t a 10 - t a -5 - t a 10 - t a ns cs low to valid data in t 39 sr 45 + t c +2t a 3tcl - 30 +t c +2t a ns cs hold after rd, wr t 40 cc 60 + t f 3tcl-15+t f ns ale fall. edge to rdcs, wrcs (with rw delay) t 42 cc 20 + t a tcl-5+t a ns ale fall. edge to rdcs, wrcs (no rw delay) t 43 cc -5 + t a -5+t a ns address float after rdcs, wrcs (with rw delay) t 44 cc 0 0 ns address float after rdcs, wrcs (no rw delay) t 45 cc 25 tcl ns rdcs to valid data in (with rw delay) t 46 sr 15 + t c 2tcl - 35 +t c ns rdcs to valid data in (no rw delay) t 47 sr 50 + t c 3tcl - 25 +t c ns rdcs, wrcs low time (with rw delay) t 48 cc 40 + t c 2tcl - 10 + t c ns rdcs, wrcs low time (no rw delay) t 49 cc 65 + t c 3tcl - 10 + t c ns data valid to wrcs t 50 cc 35 + t c 2tcl - 15 + t c ns data hold after rdcs t 51 sr 0 0 ns data float after rdcs t 52 sr 30 + t f 2tcl-20+t f ns address hold after rdcs, wrcs t 54 cc 30 + t f 2tcl-20+t f ns data hold after wrcs t 56 cc 30 + t f 2tcl-20+t f ns table 23 : multiplexed bus characteristics (continued) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. xx - electrical characteristics (continued)
ST10F167 45/61 xx - electrical characteristics (continued) figure 16 : external memory cycle: multiplexed bus, with read/write delay, normal ale data in data out address address t 38 t 44 t 10 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr, wrl, wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 14 t 46 t 12 t 48 t 10 t 22 t 23 t 44 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 54 t 52 t 56
ST10F167 46/61 xx - electrical characteristics (continued) figure 17 : external memory cycle: multiplexed bus, with read/write delay, extended ale data out address data in address t 38 t 44 t 10 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr, wrl, wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 14 t 46 t 12 t 48 t 10 t 22 t 23 t 44 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 54 t 52 t 56
ST10F167 47/61 xx - electrical characteristics (continued) figure 18 : external memory cycle: multiplexed bus, no read/write delay, normal ale data out address address data in t 38 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr, wrl, wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 15 t 47 t 13 t 49 t 22 t 23 t 13 t 49 t 9 t 43 t 43 t 9 t 11 t 45 t 11 t 45 t 50 t 51 t 54 t 52 t 56
ST10F167 48/61 xx - electrical characteristics (continued) figure 19 : external memory cycle: multiplexed bus, no read/write delay, extended ale data out address data in address t 38 address ale csx a23-a16 (a15-a8) bhe bus read cycle rd rdcsx bus write cycle wr, wrl, wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 15 t 47 t 13 t 49 t 22 t 23 t 13 t 49 t 9 t 43 t 43 t 9 t 11 t 45 t 11 t 45 t 50 t 51 t 54 t 52 t 56
ST10F167 49/61 xx.5.8 - demultiplexed bus v dd =5v 5%,v ss =0v,t a = -40 to +85 c c l (for port0, port1, port 4, ale, rd, wr, bhe, clkout) = 100 pf, c l (for port 6, cs) = 100 pf ale cycle time = 4 tcl + 2t a +t c +t f (100 ns at 20-mhz cpu clock without waitstates) table 24 : demultiplexed bus characteristics parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. ale high time t 5 cc 15 + t a tcl - 10 + t a ns address setup to ale t 6 cc 0 + t a tcl - 25 + t a ns ale falling edge to rd, wr (with rw-delay) t 8 cc 15 + t a tcl - 10 + t a ns ale falling edge to rd, wr (no rw-delay) t 9 cc -10 + t a -10 + t a ns rd, wr low time (with rw-delay) t 12 cc 25 + t c 2tcl - 25 + t c ns rd, wr low time (no rw-delay) t 13 cc 65 + t c 3tcl - 10 + t c ns rd to valid data in (with rw-delay) t 14 sr 5 + t c 2tcl - 45 + t c ns rd to valid data in (no rw-delay) t 15 sr 55 + t c 3tcl - 20 + t c ns ale low to valid data in t 16 sr 40 + t a +t c 3tcl - 35 +t a +t c ns address to valid data in t 17 sr 60 + 2t a +t c 4tcl - 40 +2t a +t c ns data hold after rd rising edge t 18 sr 0 0 ns data float after rd rising edge (with rw-delay) t 20 sr 35 + t f 2tcl - 15 + t f ns data float after rd rising edge (no rw-delay) t 21 sr 15 + t f tcl-10+t f ns data valid to wr t 22 cc 15 + t c 2tcl - 35 + t c ns data hold after wr t 24 cc 15 + t f tcl - 10 + t f ns ale rising edge after rd, wr t 26 cc -10 + t f -10 + t f ns address hold after rd, wr t 28 cc -2.5 + t f -2.5 + t f ns ale falling edge to cs t 38 cc -5 - t a 10 - t a -5 - t a 10 - t a ns cs low to valid data in t 39 sr 45 + t c +2t a 3tcl - 30 +t c +2t a ns cs hold after rd, wr t 41 cc 10 + t f tcl - 15 + t f ns ale falling edge to rdcs, wrcs (with rw-delay) t 42 cc 20 + t a tcl - 5 + t a ns ale falling edge to rdcs, wrcs (no rw-delay) t 43 cc -5 + t a -5+t a ns xx - electrical characteristics (continued)
ST10F167 50/61 rdcs to valid data in (with rw-delay) t 46 sr 15 + t c 2tcl - 35 + t c ns rdcs to valid data in (no rw-delay) t 47 sr 50 + t c 3tcl - 25 + t c ns rdcs, wrcs low time (with rw-delay) t 48 cc 40 + t c 2tcl - 10 + t c ns rdcs, wrcs low time (no rw-delay) t 49 cc 65 + t c 3tcl - 10 + t c ns data valid to wrcs t 50 cc 35 + t c 2tcl - 15 + t c ns data hold after rdcs t 51 sr 0 0 ns data float after rdcs (with rw-delay) t 53 sr 30 + t f 2tcl - 20 + t f ns data float after rdcs (no rw-delay) t 68 sr 5 + t f tcl-20+t f ns address hold after rdcs, wrcs t 55 cc -10 + t f -10 + t f ns data hold after wrcs t 57 cc 10 + t f tcl - 15 + t f ns table 24 : demultiplexed bus characteristics (continued) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. xx - electrical characteristics (continued)
ST10F167 51/61 xx - electrical characteristics (continued) figure 20 : external memory cycle: demultiplexed bus, with read/write delay, normal ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe bus (d15-d8) d7-d0 read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 20 t 14 t 46 t 12 t 48 t 22 t 24 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 55 t 53 t 57 bus (d15-d8) d7-d0 wr, wrl, wrh
ST10F167 52/61 xx - electrical characteristics (continued) figure 21 : external memory cycle: demultiplexed bus, with read/write delay, extended ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 20 t 14 t 46 t 12 t 48 t 22 t 24 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 55 t 53 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 wr, wrl, wrh
ST10F167 53/61 xx - electrical characteristics (continued) figure 22 : external memory cycle: demultiplexed bus, no read/write delay, normal ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 21 t 15 t 47 t 13 t 49 t 22 t 24 t 13 t 49 t 9 t 43 t 43 t 9 t 50 t 51 t 55 t 68 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 wr, wrl, wrh
ST10F167 54/61 xx - electrical characteristics (continued) figure 23 : external memory cycle: demultiplexed bus, no read/write delay, extended ale data out data in t 38 address ale csx a23-a16 a15-a0 bhe read cycle rd rdcsx write cycle wr, wrl, wrh wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 21 t 15 t 47 t 13 t 49 t 22 t 24 t 13 t 49 t 9 t 43 t 43 t 9 t 50 t 51 t 55 t 68 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0
ST10F167 55/61 xx.5.9 - clkout and ready v dd =5v 5%, v ss =0v,t a = -40 to +85 c c l (for port0, port1, port 4, ale, rd, wr, bhe, clkout) = 100 pf, c l (for port 6, cs) = 100 pf notes 1. these timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. demultiplexed bus is the worst case. for multiplexed bus 2tcl are to be added to the maximum values. this adds even more time for deactivating ready. the 2t a and 2t c refer to the next bus cycle, t f refers to the current bus cycle. table 25 : clkout and ready parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. clkout cycle time t 29 cc 50 50 2tcl 2tcl ns clkout high time t 30 cc 20 tcl 5 ns clkout low time t 31 cc 15 tcl 10 ns clkout rise time t 32 cc 5 5 ns clkout fall time t 33 cc 10 10 ns clkout rising edge to ale falling edge t 34 cc -5 + t a 10 + t a -5 + t a 10 + t a ns synchronous ready setup time to clkout t 35 sr 30 30 ns synchronous ready hold time after clkout t 36 sr 0 0 ns asynchronous ready low time t 37 sr 65 2tcl + 15 ns asynchronous ready setup time 1 t 58 sr 15 15 ns asynchronous ready hold time 1 t 59 sr 0 0 ns async. ready hold time after rd, wr high (demultiplexed bus) 2 t 60 sr 0 0 + t c +2t a +t f 2 0 tcl - 25 +t c +2t a +t f 2 ns xx - electrical characteristics (continued)
ST10F167 56/61 xx - electrical characteristics (continued) notes 1. cycle as programmed, including mctc waitstates (example shows 0 mctc ws). 2. the leading edge of the respective command depends on rw-delay. 3. ready sampled high at this sampling point generates a ready controlled waitstate, ready sampled low at this sampling point terminates the currently running bus cycle. 4. ready may be deactivated in response to the traili ng (rising) edge of the corresponding command (rd or wr). 5. if the asynchronous ready signal does not fulfil the indicated setup and hold times with respect to clkout (e.g. because clkout is not enabled), it must fulfil t 37 in order to be safely synchronized. this is guaranteed if ready is removed in response to the command (see note 4) ). 6. multiplexed bus modes have a mux waitstate added after a bus cycle, and an additional mttc waitstate may be inserted here. for a multiplexed bus with mttc waitstate this delay is 2 clkout cycles, for a demultiplexed bus without mttc waitstate this delay is zero. 7. the next external bus cycle may start here. figure 24 : clkout and ready clkout ale t 30 t 34 sync ready t 35 t 36 t 35 t 36 async ready t 58 t 59 t 58 t 59 waitstate ready mux/tristate 6) t 32 t 33 t 29 running cycle 1) t 31 t 37 3) 3) 5) command rd, wr t 60 4) see 6) 2) 7) 3) 3)
ST10F167 57/61 xx.5.10 - external bus arbitration vdd =5v 5%, v ss =0v,t a = -40 to +85 c c l (for port0, port1, port 4, ale, rd, wr, bhe, clkout) = 100 pf, c l (for port 6, cs) = 100 pf. notes 1. the ST10F167 will complete the currently running bus cycle before granting bus access. 2. this is the first possibility for breq to become active. 3. the cs outputs will be resistive high (pullup) after t 64 . table 26 : external bus arbitration parameter symbol max. cpu clock = 20 mhz variable cpu clock 1/2tcl = 1 to 20 mhz unit min. max. min. max. hold input setup time to clkout t 61 sr 35 35 ns clkout to hlda high or breq low delay t 62 cc 20 20 ns clkout to hlda low or breq high delay t 63 cc 20 20 ns csx release t 64 cc 20 20 ns csx drive t 65 cc -5 25 -5 25 ns other signals release t 66 cc 20 20 ns other signals drive t 67 cc -5 25 -5 25 ns figure 25 : external bus arbitration, releasing the bus clkout hold t 61 hlda t 63 other signals t 66 1) csx (on p6.x) t 64 1) 2) breq t 62 3) xx - electrical characteristics (continued)
ST10F167 58/61 xx - electrical characteristics (continued) notes 1. this is the last opportunity for breq to trigger the indicated regain-sequence. even if breq is activated earlier, the regain-sequence is initiated by hold going high. please note that hold may also be deactivated without the ST10F167 requesting the bus. 2. the next ST10F167 driven bus cycle may start here. figure 26 : external bus arbitration (regaining the bus) clkout hold hlda other signals t 62 csx (on p6.x) t 67 t 62 1) 2) t 65 t 61 breq t 63 t 62
ST10F167 59/61 xxi - package mechanical data note package dimensions are in mm. the dimensions quoted in inches are rounded. figure 27 : package outline pqfp144 (28 x 28 mm) dimensions millimeters 1 inches (approx) min. typ. max. min. typ. max. a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.133 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 22.75 0.896 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k0 (min.), 7 (max.) 144 109 d3 e 37 72 1 36 b a1 a2 a d1 d 73 108 e3 e1 e 0,10 mm .004 inch seating plane c l k l1
ST10F167 60/61 xxii - ordering information xxiii - revision history this is revision 3 of this document. the differences between rev 3 and rev 2 are as follows: update of the st logo and company name. re-formatting of the micron symbol for correct transfer onto web. preliminary data becomes data sheet. the differences between rev 2 and rev 1 are as follows: salestype temperature range package ST10F167-q6 -40 cto85 c pqfp144 (28 x 28) agpt1 timer input frequencies, resolution and periodso on page 28 table added agpt2 timer input frequencies, resolution and periodo on page 29 table added apwm unit frequencies and resolution at 20mhz cpu clocko on page 31 table added asynchronous baud rate and reload valueso on page 35 table added awatchdog timer rangeo on page 36 table added abootstrap loadero on page 38 text changed page format of the datasheet cover changed
ST10F167 61/61 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http ://www.st.com

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